Most systems currently used are operated by being synchronized with a clock. Therefore, a quality of the clock is very important in these systems.
A clock and data recovery (CDR) circuit is a key circuit configured to correctly recover a clock required by a system in the data communication field and transmitted data from a data stream. In order to read data at an optimum position, a phase of the clock needs to be shifted to an optimum position for reading data, which can be accomplished by making the phase of the clock agree with a phase of data. Therefore, a circuit capable of freely controlling a phase of a clock is needed. As examples of a circuit for controlling a phase of a clock, a phase-locked loop (PLL) and a delay-locked loop (DLL) may be used.
FIG. 1 is a configuration view showing a general configuration of a delay-locked loop.
A delay-locked loop includes a delay unit 110 that delays an input clock (IN_CLK) to generate an output clock (OUT_CLK), a replica delay unit 120 that outputs a feedback clock (FB_CLK) by delaying the output clock (OUT_CLK) as much as a delay value within a system to which the delay-locked loop is applied, and a phase comparison unit 130 that compares the input clock (IN_CLK) with the feedback clock (FB_CLK) and increase or decrease the delay value of the delay unit to make the input clock (IN_CLK) equal to the feedback clock (FB_CLK).
The delay unit 110 increases or decreases its own delay value under the control of the phase comparison unit 130. However, the delay value of the delay unit 110 is limited and cannot be infinitely increased or decreased infinitely. Therefore, an operation range of the delay-locked loop is limited by the limit of the delay value of the delay unit 110.
Not only the delay-locked loop but other circuits that need to increase or decrease a delay value during an operation also have such a problem.
The present disclosure is suggested to solve a conventional problem described above and provides a variable delay circuit capable of infinitely increasing or decreasing a delay value and a delay-locked loop circuit including the variable delay circuit.